As DRAMs increase in memory cell density, there is a continuous challenge to maintain a sufficiently high storage capacitance despite decreasing cell area. It is important that storage node capacitor cell plates be large enough to retain an adequate charge or capacitance in spite of parasitic capacitances and noise which may be present during circuit operation. The principal way of increasing cell density is through cell structure techniques. Such techniques include three dimensional cell capacitors, such as trenched or stacked capacitors.
One way of increasing capacitance is to roughen various surfaces of the capacitor, thereby maximizing the area for stored capacitance. Such techniques are shown by way of example in T. Mine et al., "Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMs", taken from Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo, pp. 137-140, 1989; H. Watanabe et al., "A New stacked Capacitor Structure Using Hemispherical-Grain (HSG) Poly-Silicon Electrodes", taken from Extended Abstracts of the 22nd (1990 International) Conference on Solid State Devices and Materials, Sendai, pp. 873-876, 1990;p Hayashide et al., "Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode" taken from Extended Abstracts of the 22nd (1990 International) Conference on Solid State devices and Materials, Sendai, pp. 869-872; and Fazan et al., "Thin Nitride Films on Textured Polysilicon to Increase Multimegabit DRAM Cell Charge Capacity", taken from IEEE Electron Device Letters, Vol. 11, No. 7, Jul. 7, 1990. No admission is made as to whether each of these documents is prior art to this submission.
With a conventional stacked capacitor, the capacitor is formed immediately above and electrically connected to the active device area of the associated MOS transistor of the memory cell. Typically, only the upper surface of the lower storage polysilicon node of the capacitor is utilized for capacitance. However, some attempts have been made to provide constructions to increase capacitance, whereby the back side of one capacitor terminal is used to store a charge. Such is shown by way of example by T. Ema et al., "The Numeral 3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS" IEDM Tech. Digest, pp. 592-595, 1988 and S. Inoue et al., "A spread stacked capacitor (SSC) cell for 64M bit DRAMS", IEDM Tech. Digest, pp. 31-34, 1989.
The article by Ema et al. discloses a construction for 16 and 64 megabit DRAMS. FIGS. 1 and 11 from this article illustrate a vertically rising capacitor construction having a plurality of horizontal fins, both sides of which are utilized for stored capacitance. The article to Inoue et al. utilizes spread of horizontal area for three dimensional stacked capacitor construction. Both such processes significantly add tedious processing steps over conventional techniques for creation of three dimensional stacked cell capacitors, and require that tight tolerances be adhered to in contact alignment.
It would be desirable to improve upon these and other processes in providing three dimensional stacked capacitors which maximize capacitance.